This invention generally relates to clock recovery circuits, and more specifically relates to a circuit which provides continuous correction/adjustment of the duty cycle of a clock signal.
In clock recovery applications, such as in serial data communications, the data which is received contains clock alignment information. Clock recovery circuits enable the capture of the recovered data by using this information to align a clock to the received data. The duty cycle of this aligned clock can be critical to the error margin of the data capture.
Often times, a clock signal has a duty cycle which is distorted due to semiconductor process error. Often in high speed integrated circuits, the duty cycle of a CML clock signal can be critical to performance. The duty cycle of a clock can either determine critical timing margins or be used to adjust timing, depending on the application. In one application, a clock recovery circuit generates a clock whose falling edges are aligned to the transitions in the received data signal. When these edges are aligned, a perfect duty cycle would have a rising edge which is perfectly centered on a data bit. Any movement to either side of this perfect alignment, caused by an imperfect duty cycle, affects the robustness of the data capture ability. FIG. 1 illustrates a received clock signal 10 and an aligned clock signal 12, wherein the aligned clock signal 12 has a perfect duty cycle, while FIG. 2 illustrates a received clock signal 14 and an aligned clock signal 16, wherein the aligned clock signal 16 has a degraded duty cycle.
Because the duty cycle of a clock signal can be so critical to performance, it is important to recover a clock signal which has no duty cycle distortion.
Data capture circuits do not provide for the continuous analog correction of duty cycle. Instead, many current data capture circuit designs build in a margin to allow for duty cycle distortion. However, allowing for duty cycle distortion reduces the robustness of the design.
A general object of an embodiment of the present invention is to provide a circuit which is configured to correct or adjust the duty cycle of a clock signal.
Another object of an embodiment of the present invention is to provide a circuit which is to configured to continuously and automatically correct the duty cycle of a clock signal without employing a built in margin which allows for duty cycle distortion.
Still another object of an embodiment of the present invention is to provide a circuit that includes a differential pair of transistors that is configured to pull at least one of the inputs of a differential circuit down in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a circuit that is configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to pull at least one of the inputs of the differential circuit down in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.